Reclaiming Performance and Energy Efficiency from Variability

This paper presents methods for addressing two sources of variability in the context of microprocessors within-die process variability and dynamic thermal variability and shows the improvements in performance and energy efficiency obtained by applying them to a globally asynchronous, locally synchronous (GALS) microprocessor design. The GALS design style partitions the core into several independently-clocked domains, which provides a natural granularity for variability to be addressed at. Process variability is addressed by observing that each domain has fewer critical paths than the processor as a whole, shifting their maximum frequency distributions towards higher speeds. Meanwhile, the detrimental effects of thermal variability are reduced by isolating the effects of thermal hotspots on delay to the domains they occur in. We simulate a subset of the SPEC2000 benchmarks, comparing the baseline GALS architecture against a version that accounts for the reduction in the number of critical paths per domain, a version that scales the clock speed of each domain based on the slack between its temperature and the maximum operating temperature of the core, and a final version that does both. These schemes achieve improvements of 2.0%, 9.5%, and 11.4% in execution time and 4.4%, 16.0%, and 20.0% in energy-delay, respectively.